The field of this invention relates to an integrated circuit device, a synchronisation module, an electronic device and a method therefor. The invention is applicable to, but not limited to, a method and apparatus for synchronising an asynchronous clock request.
In the field of digital electronic devices, a synchronous circuit is a digital circuit in which the various parts are synchronized by a clock signal. For many digital applications, for example within the field of mobile communications etc, digital electronic devices are required to meet tight power consumption restrictions.
Clock gating is a popular technique used in many synchronous circuits for reducing dynamic power dissipation. Clock gating saves power by adding logic to a circuit to ‘prune’ the clock tree. Pruning the clock tree disables portions of the circuitry so that the storage elements do not have to switch states. When not being switched, the switching power consumption of a storage element goes to zero, and only leakage currents are incurred. An additional benefit of clock gating is that it also enables noise within the electronic device to be reduced.
Typically, a digital electronic device may comprise multiple clock domains, wherein each clock domain comprises one or more synchronous circuits synchronized to at least a common reference clock signal. Synchronization between different clock domains is a common requirement in digital designs. However, when the clock domains are discontinuous in order to keep the power and noise to a minimum, for example through clock gating or the like, maintaining synchronization between the different clock domains becomes difficult. For example, asynchronously ‘waking-up’ a gated clock domain can lead to a ‘runt’ pulse within the initial clock cycle. For example, such a runt pulse may comprise a partial pulse capable of triggering state switches within the clock domain, but of insufficient duration to allow sufficient time for signals to propagate fully through the clock domain logic.
Maintaining at least one clock alive within each clock domain enables synchronization to be maintained between different clock domains, and thus helps to avoid runt pulses. For example, a reference clock may be maintained within each clock domain, with clock gating being implemented within downstream circuitry to reduce power and noise. However, this approach inherently limits the effectiveness of clock gating within the clock domains since a reference clock signal is required to be maintained for each clock domain.
Implementing clock gating at the source end of the clock supply enables the benefit of such clock gating in relation to power consumption of the respective clock domain to be maximised. Conventionally, such source end clock gating requires sequential logic to be provided at the clock source to enable synchronous un-gating of the supply clock in response to an asynchronous request, and thus alleviate the problem of runt pulses. However, such sequential logic at the clock source can generate unwanted noise in sensitive circuits. However, omitting such sequential logic at the clock generator could lead to ‘runt’ pulses at the first cycle following asynchronous un-gating of the clock supply.
An alternative method for removing runt pulses comprises clocking a request signal by the output of a control module to generate a request and using a set of, say, flip-flops to delay the output of the clock gate to remove the runt pulse. However, such a method involves the flip-flops being clocked from non clock signals. Attaching non-clock signals to clock pins is a potential problem as it may violate design rules, is considered bad practice and may be prone to glitches if the source is from decoded logic.
Metastable filtering is a simple approach for continuous asynchronous clocks, for example using a pair of flip-flops in sequence. The reference clock can then be gated locally by the synchronized control signal. However, such a solution requires continuous clocks since the sending and receiving clocks must be on at the same time, again limiting the effectiveness of clock gating.
Thus, a need exists for an improved apparatus for synchronising an asynchronous clock request and method of operation therefor.